The present invention relates to a semiconductor device.
Semiconductor devices generally include a substrate having external connection terminals, a semiconductor chip provided over the substrate, and connection bumps connected to the external connection terminals.
The external connection terminals are formed by sequentially forming a first electroless plating layer, a second electroless plating layer, and a third electroless plating layer on a terminal portion formed on a surface of the substrate (see, for example, Japanese Patent Laid-Open Publication No. 2005-256128).